I am having a bit of a trouble with the austosync functionality "10 = sync on DPLL phase lock".
My configuration is in principle:
- Reference: 1PPS from a GPS
- DDS frequency 240 MHz
- Loop bandwidth 50 mHz
- DPLL output frequency 1 Hz
I can observe the following behaviour:
Every time the DPLL achieves phase-lock, the positive edge of the 1Hz output signal is approximately +/- 50ns within the positive edge of the reference signal coming from the GPS. The 1Hz DPLL output signal keeps this skew as long as it is locked. However after resetting the DPLL, it will end up at with a different skew in relation to the average to the GPS reference pulse.
The jitter of the GPS reference pulse is with 15ns very small and with the current DPLL setting "sync on DPLL phase lock", I would assume it actually synchronises the output divider on the average of the GPS input reference variation.
As the skew is different after every reset, it is hard to compensate for it in Software.
What can I do to minimise or even remove this random skew and make sute the positive edge of the 1Hz DPLL output is located in the center (average) of the reference pulse comming from the GPS?