I'm using the AD7626 within my design with the input circuitry as proposed in the datasheet (single to differential configuration with the proposed amps). The complete control of the ADC (cnv, clk, data transfer to PC) is done by a FPGA (Cyclone 3). Unfortunately, when I'm converting a voltage ramp, I see spikes within my output signal. These spikes are not due to timing or transfer problems but they seem to be voltage dependent (this is proven by the two ramps with different slopes as well as the sinusoidal signals - one in between two error voltages and one at an error voltage - attachment!!). So, the error seems to have its origin within the ADC, probably an error during a bit switchover?!
Do you have ever seen such a problem and do you have any possible solution to it?
I followed the specified startup conditions as well as the correct EN-signaling...