I use the AD9548 in own design and there are some initial points:
- 1PPS (4 uS pulse width) on Reference A
- Just one Profile 0
- 24.5757 MHz CMOS TCXO for SYSCLK
- SYSCLK 933.8766 MHz
- DDS 176.9472 MHz
- Outputs are 58.9824 MHz, 5.89824 MHz and 32.768 kHz.
The DPLL loop filter settings: loop BW of 20 mHz, 70 deg pm, and a 3rd pole offset (at -3dB) of 0.5 Hz.
At first, I checked out how the AD9548 works in free-run mode. Result was well.
Then I wrote the rest of the registers. 3 - 4 minutes later, reading appropriate status registers, I got: SYSCLK is locked and stable, Reference is valid, History available.
DPLL is active, but is not locked. I watched the same on an oscilloscope.
What is wrong?
Help me, please.
Silicon revision is 0xC6.
Device ID is 0x48.
P.S. I would like to avoid buying the evaluation board.