This is very frustrating. One day my PLL setup was working fine, basically identical to the example code, and the next day it doesn't work! Here is what I am now getting from *PMCTL upon reset:
0x31000 (= 11 0001 0000 0000 0000)
According to the HRM Table A-3. PMCTL Register Bit Descriptions, bits 5-0 have a reset value = CLK_CFG[1:0], and likewise, 17-16 have a reset value = CLK_CFG[1:0]. As you can see from above, they are unequal. Not only that but the values for 17-16 point to an invalid pair according to the documentation.
My symptom of this problem is that I cannot change the CCLK to be anything but CLKIN!