AnsweredAssumed Answered

AD9361 Rx Path

Question asked by aveljkovic on Mar 28, 2014
Latest reply on Apr 8, 2014 by mhennerich

Hi All,


We use AD-FMCOMMS2-EBZ AD9361 RF hardware evaluation board along with Xilinx VC707 board. Our design does not include Microblaze processor and we control AD9361 from PC. PC and VC707 board  are connected over gigabit ethernet and PC sends AD9361 register read/write commands to VC707. VC707 parses those commands and forwards them to AD9361 using SPI lines.


Starting point for our PC software was AD9361 NO-OS SOFTWARE from website.

We successfully set up BBPLL, RFPLL Synthesizers, Digital Data Interface, TX Baseband Filter Tuning, TX Secondary Filter Calibration, TX Attenuation, Tx Quadrature Calibration.

We set BBPLL frequency to 983.04 MHz and set BBPLL divider to 2, so ADC and DAC works at 245.76MHz (at least we think so).  Our VC707 design requires 245.76MHz clock, so we bypass

all digital filters. We use QPSK and sine source for AD9361 transmitting side and wrap around it to receiving side. Transmitting side works fine according to QPSK and Sine spectrum waveform on Spectrum Analyzer. We have issues with receiving side and in the text bellow we will try to describe consequences. TX LO Frequency is set to 2400MHz and transmitting side produces sine wave at 1MHz upconversion frequency.  When we directly connect transmit and receive part of AD9361 we get large LMT overload, so we set LMT overload high tresh to 1024 and LMT overload low tresh 0 and put 20dB external attenuator.


We have all of following parts in our code: 

-Program Mixer GM Sub-table

-Program Rx Gain Tables

-Setup Rx Gain Control

-RX Baseband Filter Tuning

-RX TIA Setup

-ADC Setup


but we cannot get proper spectrum waveform in FPGA after wrapping around (either QPSK or Sine). We have chipscope in our design, after iddr pool, and we are processing the captured data in Matlab, we get bad spectrum image. Both, sine and QPSK, are immersed in noise(sine is about 20dB above noise). Also there is a huge DC component about 40dB above noise. Look the picture

spectrum_full.jpg in the attachment. Pictures timing_real.jpg and timing_imag.jpg show the timing waveforms of i and q axis while pictures spectrum_real.jpg and spectrum_imag.jpg show their spectrum images respectively. You can see glitches at the same bit(0.25 in size), and we have tried to solve it by adjusting its idelay value, but without success. RX LO Frequency is set to 2410MHz, so the sine has the right position in the spectrum.


We suppose that proper sigma-delta ADC, digital filters or gain configuration can solve our issues.

When we turn on just one RX digital filter(either RX HB3 or RX HB2 or RX HB1) we get the same DATA_CLK on FMC line. How is that possible? If we turn on two RX digital filters, DATA_CLK is decreased 2 times, instead 4 times. Can the configuration,

when all RX digital filters are turned off, cause the issues?


We have tried two gain modes, MGC and AGC Slow Attack. How can we change the gain in MGC mode? Is the changing gain table address the right way(register 130)? We have also monitored CH1 Lg LMT Ovrg, CH1 Lg ADC Ovrg and CH1 Sm ADC Ovrg bits and noticed that changing gain table address did not reset them.


How can we configure sigma-delta ADC? Does the configuration of ADC Small Overload Threshold and ADC Large Overload Threshold just give us information about signal range or it has influence on performance? We set MGC mode and, by monitoring CH1 Lg ADC Ovrg and CH1 Sm ADC Ovrg bits, determine ADC tresholds.



Any help would be most welcome.


Thank you.