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AD8362 CLPF Filter Capacitance Trade Offs

Question asked by roadrunner Employee on Jul 22, 2010
Latest reply on Jul 23, 2010 by enash

We have a carrier signal at 200MHz driving the AD8362.  AM modulation is from 30Hz to 20kHz.  To “remove” the modulation signal from the detected DC voltage, we have ~5.7uF on pin CLPF.  This reduces the AC component on the Vout line to ~300mVp-p which is still too high.  I would like to see less than 100mV.  50mV would be great.


If I increase the capacitance on the CLPF, the response time is too slow (mainly on the falling edge).  I have tried a number of analog things external to the detector with no good solutions.


The last thing I was trying was to reduce the voltage on the Vtgt pin to attempt to reduce the AC ripple.  This did help a lot but it also pushed out the time a lot too.



Is there a solution?

Explain how the Vtgt pin works and why the falling edge time increased with decreasing Vtgt voltage.

Any suggestions will be appreciated.