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ADAU1442 sample rate converter and input jitter

Question asked by AlexvW on Mar 28, 2014
Latest reply on Apr 13, 2014 by Yagami

Hi all,

 

I am designing a system using the ADAU1442, which I need to interface with sereval SPDIF receivers. To maximize performance, I want to implement a jitter attenuator on the I2S signals before they enter the ADAU1442.

 

In order to reduce the jitter, should I only 'clean' the BLCK signal, or also the LRCLK signal or perhaps both of these signals comming from the SPDIF receiver?

 

Thanks and kind regards,

 

Alex

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