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AD9361 aux ADC logical functionality

Question asked by yanivs on Mar 27, 2014
Latest reply on Apr 9, 2014 by mhennerich

Hi,

 

Can you please share the logic behind the following code (as well as the function ad9361_dig_tune) in ad9361.c.

What exactly is the Auxiliary ADC being used for? Can you provide any reference to any document?

Also, any register spec of the Aux ADC will help.

 

Yaniv

 

 

int32_t ad9361_post_setup(struct ad9361_rf_phy *phy)

{

...

          axiadc_write(st, ADI_REG_CNTRL, rx2tx2 ? 0 : ADI_R1_MODE);

          tmp = axiadc_read(st, 0x4048);

 

          if (!rx2tx2) {

                    axiadc_write(st, 0x4048, tmp | BIT(5)); /* R1_MODE */

                    axiadc_write(st, 0x404c, 1); /* RATE */

          }

  else {

                    tmp &= ~BIT(5);

                    axiadc_write(st, 0x4048, tmp);

                    axiadc_write(st, 0x404c, 3); /* RATE */

          }

 

          for (i = 0; i < conv->chip_info->num_channels; i++) {

                    axiadc_write(st, ADI_REG_CHAN_CNTRL_1(i),

                              ADI_DCFILT_OFFSET(0));

                    axiadc_write(st, ADI_REG_CHAN_CNTRL_2(i),

                              (i & 1) ? 0x00004000 : 0x40000000);

                    axiadc_write(st, ADI_REG_CHAN_CNTRL(i),

                              ADI_FORMAT_SIGNEXT | ADI_FORMAT_ENABLE |

                              ADI_ENABLE | ADI_IQCOR_ENB);

          }

 

          ret = ad9361_dig_tune(phy, 61440000);

...

}

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