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ADDI7004 DOUT bit count problem.

Question asked by shahrilhafiz.zainol@vie.com.my on Mar 26, 2014
Latest reply on Apr 3, 2014 by shahrilhafiz.zainol@vie.com.my

Hi,

 

I have confirmed that the ADC IC response to all my SPI configuration. I can control the ADC to work on single port or dual data port. I can configured the skew and the shifting between analog sampling clock and the digital dataout.The only problem I face now is LVDS DOUT always give 7-bits data out instead of 8-bits. I still can't point out if this problem because of the timing issue or LVDS signal quality(ringing effect?). Below are the captured images.

 

On the below waveform, grey wave belong to LVDS TCLK(data clock reference) while yellow are the serial data out from ADC to FPGA.

I use 0x8080 as a test pattern data. This pattern data wil serially shift out from ADC LVDS to FPGA. Yellow spike is a MSB which carry 0x8 value.The next spike should appear after 4-cycles of TCLK.(Data capture using double data rate which is 8-bits in 4 cycles TCLK). But it is not happen. Next MSB always appear after 7-bits data serially shift out as can be seen in below waveform.

Inline image 1

 

Below waveform using test pattern data as 0x5555, some of the bits are just dissepear or not syncronize with the TCLK.

Inline image 2

 

Waveform with test pattern data of 0x5F5F, small yellow spike carry value of 0x4, and bigger yellow spike should carry 0x1 and 0xF which combined to be 0x5F.

Inline image 3

 

I did test tuning the termination resistor from 100ohm to something lower, however its not fix the problem, it just attenuate the LVDS data waveform magnitude to smaller. Do we need to add some series resistor on the LVDS bus beside termination resistor only if this is ringing effect? I have play with most of ADC configuration register but none change this.

 

Thanks,

Shahril

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