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ADV7842, in: COMP (576i), out: bt.656(8 bit)

Question asked by Sasa on Mar 26, 2014
Latest reply on Apr 1, 2014 by Sasa



Chip: ADV7842


Input: component YPrPb 576i@50

     PRIM_MODE[3:0], IO.0x01[3:0] = 1;        // Component Mode (p.40)

     VID_STD[5:0], IO.0x00[5:0] = 000011b;    // SD 2x1 625i, 720 x 576i (p.41)

     V_FREQ[2:0], IO.0x01[6:4] = 001b;          // 50 Hz (p.45)


Output: bt.656, 8 bit

     OP_FORMAT_SEL[7:0], IO.0x03[7:0] = 0x00;          // 8-bit SDR ITU-656 mode


In this mode I get pixel clock LLC = 13.5MHz – must be 27MHz (when I work from CVBS-input with default settings of DLL I have LLC=27MHz). If I set LLC=27MHz (method see below) I see picture.


Why I have LLC=13.5MHz (instead 27) in this mode and what must I do?



In forums (no UserGuide “UG-214.pdf”) I found, that exist two controls for LLC:


1.          Use DPLL (p.55):

     LLC_DLL_EN, IO.0x19[7] = 1;          // Enable LLC DLL, default = 0

     LLC_DLL_MUX, IO.0x33[6] = 1;        // Muxes the DLL output on LLC output, default = 0

     LLC_DLL_DOUBLE, IO.0x19[6] = 1;  // Double LLC clock frequency, default = 0 (absent in “UG-214.pdf”)


2.          Use register IO.0xDD (absent in “UG-214.pdf”):

     MAN_OP_CLK_SEL_EN, IO.0xDD[7] = 1;  // 0 - Automatic output clock selection based on OP_FORMAT_SEL, default

                                                                                                          // 1 - Manual output clock selection as defined by MAN_OP_CLK_SEL[2:0].

     MAN_OP_CLK_SEL[2:0], IO.0xDD[6..4] = 001b;          // 2x data clk (2x CP_CLK) – DON’T WORK!!!

     MAN_OP_CLK_SEL[2:0], IO.0xDD[6..4] = 101b;          // Reserved. Do not use. – OK WORK (from forums)!!!


The 1-st method give me LLC=27MHz and picture.

The 2-nd method with MAN_OP_CLK_SEL[2:0] = 001b (2x CP_CLK) don’t work, but code 101b (Reserved) give LLC=27MHz and I see picture.

In library "ADV7842_API_Library-Rel1.55.2.1" method 2 (MAN_OP_CLK_SEL_EN) no used...


Best regards,