Hello. I would like to implement a fixed frequency generator of 12.2GHz using the ADF41020. In order to improve the in-band phase noise (within loop bandiwdth), I intend to use 50MHz phase detector frequency, using an external 100MHz Reference frequency (R divider =2)

However, when I try to simulate the 12.2GHz fixed frequency PLL using ADISimPLL V3.41, the software prompted me the following error

" ADF41020 is incompatible with these requirements

Using P=8 Prescaler exceeds max prescaler output frequency of 330MHz

P=16 Prescaler cannot achieve desired channel

P=16 Prescaler cannot achieve N value of 61

P=64 Prescaler cannot achieve N value of 61

No valid prescaler option could be found"

I could understand P=8 problem, but with P=16, the prescaler output frequency shall be 190MHz (below the prescaler max frequency). With P=16, B=3, A=13=> we should be able to achieve the N=244 [ i.e. 4*(3*16+13)]. Why does the software prompt us that the N value cannot be achieved?

Anyone could help me? Appreciate your help on this matter

Regards

lguancho

For the dual modulus prescaler,

N = B*P+A

with A <= B

this last requirement is hidden on the ADF41020 datasheet at the bottom of P11.

So you can't achieve 61 with a 16/17 prescaler as B=3 and A=13.

This is to do with how the dual modulus prescaler operates. Using the 16/17 prescaler, you can only achieve your final division by dividing in chunks of 16 or 17:

To divide by 48 you simply divide by 16 three times.

To divide by 49 you divide by 16 twice then by 17 once.

To divide by 50 you divide by 16 once then by 17 twice

To divide by 51 you divide by 17 three times

You can't divide by 52, or any number until you get to 64, which you achieve by dividing by 16 four times.