Hello. I would like to implement a fixed frequency generator of 12.2GHz using the ADF41020. In order to improve the in-band phase noise (within loop bandiwdth), I intend to use 50MHz phase detector frequency, using an external 100MHz Reference frequency (R divider =2)
However, when I try to simulate the 12.2GHz fixed frequency PLL using ADISimPLL V3.41, the software prompted me the following error
" ADF41020 is incompatible with these requirements
Using P=8 Prescaler exceeds max prescaler output frequency of 330MHz
P=16 Prescaler cannot achieve desired channel
P=16 Prescaler cannot achieve N value of 61
P=64 Prescaler cannot achieve N value of 61
No valid prescaler option could be found"
I could understand P=8 problem, but with P=16, the prescaler output frequency shall be 190MHz (below the prescaler max frequency). With P=16, B=3, A=13=> we should be able to achieve the N=244 [ i.e. 4*(3*16+13)]. Why does the software prompt us that the N value cannot be achieved?
Anyone could help me? Appreciate your help on this matter