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Re-org Ext Memory causes CPLB miss? (BF561)

Question asked by Laz on Jul 21, 2010
Latest reply on Jul 22, 2010 by Laz

I just modified a working project to put my video buffers into different banks of the SDRAM, per EE-276.  As soon as I tried to write to the memory in one of the upper banks, I get a cplb_miss_without_replacement error.  I can still write to the lowest bank.  I am not doing anything active with the cache or cplb tables.  I am using the BF561 EZ-KIT with AV Extender and Aptina camera.  Honest, I didn't change anything else!  I've checked the map file and the video buffers ended up where I wanted, and the code stayed in the default lowest bank.  Any ideas?

 

Here is the relevant part of the LDF.

 

   MEM_L2_SRAM             { TYPE(RAM) START(0xFEB10000) END(0xFEB1FFFF) WIDTH(8) }
   MEM_ASYNC3              { TYPE(ASYNC3_MEMTYPE) START(0x2C000000) END(0x2FFFFFFF) WIDTH(8) }
   MEM_ASYNC2              { TYPE(ASYNC2_MEMTYPE) START(0x28000000) END(0x2BFFFFFF) WIDTH(8) }
   MEM_ASYNC1              { TYPE(ASYNC1_MEMTYPE) START(0x24000000) END(0x27FFFFFF) WIDTH(8) }
   MEM_ASYNC0              { TYPE(ASYNC0_MEMTYPE) START(0x20000000) END(0x23FFFFFF) WIDTH(8) }

 

   // EZ_KIT = 64MB
   MEM_SDRAM               { TYPE(RAM) START(0x00000004) END(0x00ffffff) WIDTH(8) }
  
   /*$VDSG<insert-new-memory-segments>                          */
   /* Text inserted between these $VDSG comments will be preserved */

   // EZ KIT
   MEM_SDRAM_BANK1               { TYPE(RAM) START(0x01000000) END(0x01ffffff) WIDTH(8) }
   MEM_SDRAM_BANK2               { TYPE(RAM) START(0x02000000) END(0x02ffffff) WIDTH(8) }
   MEM_SDRAM_BANK3               { TYPE(RAM) START(0x03000000) END(0x03ffffff) WIDTH(8) }
  
   /*$VDSG<insert-new-memory-segments>                          */

 

...

 

Each typical memory assignment

 

// dgl create these new sections
      sdram_bank1
      {
         INPUT_SECTION_ALIGN(4)
         /* Place shared program code in the section sdram_shared.
         * and use the LDF RESOLVE command from Core B.
         */
        
         /*$VDSG<insert-input-sections-at-shared-sdram>         */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-shared-sdram>         */
        
         INPUT_SECTIONS($OBJECTS_CORE_A(sdram_bank1) $LIBRARIES_CORE_A(sdram_bank1))
        
         /*$VDSG<insert-input-sections-at-the-start-of-sdram-A>  */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-start-of-sdram-A>  */
        
        
         /*$VDSG<insert-input-sections-at-the-end-of-sdram-A>   */
         /* Text inserted between these $VDSG comments will be preserved */
         /*$VDSG<insert-input-sections-at-the-end-of-sdram-A>   */
        
      } > MEM_SDRAM_BANK1

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