I have several question about AD5391 Power-on reset and power up sequence.
1) Power-on reset is powered by DVDD?
2) What DVDD voltage make start Power-on reset procedure?
3) For avoiding un-expected analog ouput, should power up AVDD after DVDD? (Power-on reset might prevent unexpected analog output during power up sequence?)
4) About AD5391 datasheet page 37,
The AD539x contains an internal power-on reset circuit with a 10 ms brown-out time. If the power supply ramp rate exceeds 10 ms, the user should reset ...(cont.)
It seems that Power-on reset will not work because too slow DVDD ramp-up over 10ms. My understanding is correct?
Is large distance between AVDD and DVDD power on timing also may not start Power-on reset?
5) If RESET and CLR pins are external pull down at the start of power up system, Power-on reset will work?
(RESET and CLR also connected FPGA, after finish FPGA configuration, FPGA make these pins high.)
Thank you for your help in advance.