we are currently working on a FPGA (Altera Cyclone V)
interfacing the ADV7619 Video Chip, and we are facing
an issue for which you will may be able to help us.
The chip delivers correctly HDMI 1080p @ 50Hz and 60Hz
with our registers configuration (see below), but fails to deliver
correct HDMI Signaling @ lower frame rates : 24, 25 or 30Hz :
- the received clock in the FPGA is 74,25MHz, which is correct.
- but the VSYNC / HSYNC / DE signals are not stable
(DE not a burst of 1920 pixels, HSYNC and VSYNC containing glitches, etc ...)
like if the ADV7619 was not locked to the incoming video stream.
The video registers configuration is the recommended one :
(we don't need Free Run mode)
VID_STD = 0x02
If necessary I can provide more details with waveforms showing the issue.
The board used is a custom one, and we don't have the AD Eval Board.
Many thanks for your help