I wonder if there is any signal/interrupt which tells when the ADV is ready decoding a frame ?
Rini van Zetten
Your question is unclear. Do you meant that, when decoding, there is 1) a signal that the part is ready to take a new frame for decoding or 2) decoding is finished. It also depends what mode you are using the part in.
Thanks for replying.
I want to now when decoding is finished (option 2).
We use the decoder in slave mode, Custom Specific Video Format.
What other information do you need ?
In that mode-- it'll come out based on the video timing if it's ready or a black frame if it's not. There isn't any signal that tells you. The rule of thumb is that if the entire codestream to be decoded is inside the part by 1/3 of a tile time before the next VSYNC, it'll come out on the next VSYNC.
In our set-up we use a FPGA which generates the HSync/VSyncs.
What i want to achieve is to signal the fpga when it can generate a new sync to read out the frame.
This works fine when i wait for example 30 ms after sending the last byte, but i want to know the minimum time we have to wait to shorten the latency.
Other question. In your first answer situation 1 : Is the part ready to receive new data when the fifo threshold condition exist (EIRQFLG register). What i see is that bit is set immediate after sending a frame.
As I said, there is no signal like what you want. Custom mode is assuming a consistent video timing. If you follow the rule of thumb I mention, you should be fine.
The Threshold interrupt (or burst DMA signal) is tied to space in the input fifo. It has nothing to do with anything else going on in the chip directly. If it has space, it'll ask for data even if it's not about to use it. It's generally better to give it one tile worth of data per tile time and then nothing until after the VSYNC even if it has space. This also depends on having a consistent video timing.
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