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AD9915 SYNC_CLK phase

Question asked by nmrcarl on Mar 19, 2014
Latest reply on Mar 24, 2014 by sitti

In the AD9915 data sheet there is some discussion of multi-chip synchronization, including the procedure to synchronize with an external device during the DAC CAL operation using the SYNC_IN pin.

 

My question concerns the effect of this operation on the SYNC_CLK output (used to clock modulation data into the parallel port):  is the phase of SYNC_CLK affected by the external device synchronization?  For example, if I have a 100 MHz clock derived from the same oscillator as REF_CLK, and I compare this signal with SYNC_CLK, should they always have the same phase?  What if I change the value of the SYNC_IN delay in register USR0?

 

Thanks,

Carl

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