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getting out of sync in link ports

Question asked by rav on Jul 20, 2010
Latest reply on Aug 10, 2010 by rav


We're connecting an FPGA to TigerSHARC ADSP-TS201S through 2 of its link ports.

I have a question regarding the link port protocol:

1) can the clk_out pin be idle in the middle of a Quad word transffer?

2) as I understand there is no way to sync on the start of a Quad Word. If from some reason (lets say noise), I received a false rise and fall of clk_out, Is there a way that I can be synced back on the start of the next Quad Word?

If not, is there a work arround if such case happens?