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AD9361_Tx_Path gain setting

Question asked by Raveendra on Mar 18, 2014
Latest reply on Apr 2, 2014 by tlili



I am using the AD9361 chip for my application. First i am working on Transmitter Path, for this i enabled clock output and i configured BBPLL, RF PLLs in both sections and i want to see LO leakage in TX output. How much level we can get in Tx output port of LO signal?


I want you know how to control the gain/attenuation of Tx path? and how much LO level will be generated by PLL to mixer?