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A question about AD9915 (3.5 GHz input clock for PLL Disable mode)

Question asked by Sercan on Mar 17, 2014
Latest reply on Mar 25, 2014 by Sercan



For AD9915, at the datasheet (Rev.D) we see the belows:



When the direct input path is selected,

the REF_CLK/REF_CLK pins must be driven by an external

signal source (single-ended or differential). Input frequencies

up to 3.5 GHz are supported.



pg.5 / Table.2

limits the input frequency to 2.5 GHz. (As the attached figure.)



When we apply 3000 MHz / 3500 MHz AD9915 is functioning for PLL Disable mode. For profile mode for some output frequencies.
Sure not be able to test all the conditions.

We suppose to use DDS in PLL Disable mode, and have AD9915 Ev.Board only.

So, if we have an ability to use the AD9915 in PLL Disable mode with 3 GHz (or upto 3.5 GHz, like page-21), it will be a nice plus for us.

Sure without losing any functionallity.


Can you please check this condition and let us know if there are any functionallity losses for the 3  - 3.5 GHz input clocking for PLL Disable mode of the AD9915?


Thanks & regards,

Sercan Egilmezkol