Please teach me AD7699.
The following description is on datasheet P5.
DIN Valid Setup time from SCK Falling Edge(tSDIN) 5ns MIN.
DIN Valid Hold Time from SCK Falling Edge(tHDIN) 5ns MIN.
I checked figure of data sheet P23 and P25.
Rising edge of SCK is trigger of tSDIN,tHDIN in this Figure.
How should be interpreted it?