Hello SDR experts.
I have two questions and really appreciate your answers to this.
(1) In the AD9361 data sheet rev.D fig. 1, assuming Rx_Lo = Tx_Lo and all freq, clocks etc. are equal. If an exact signal is inputted to (say) to Rx1A and to Rx2A, can the system guarantee same delay and phase out at Tx1A and Tx2A.
(2) Will it work and function properly by fitting e.g. 2x AD-FMCOMMS2-EBZ or (2x AD-FMCOMMS3-EBZ) etc. boards hence one to the LPC and one to the HPC onto say a znyq ZC706 or any other Xilinx eval-board with 2 FMC connector (e.g. LPC and a HPC) such as the KC705, KC707 etc.
Thanks and Regards,