Hello. I am using an AD9361 (FMCOMMS2) on a FPGA development environment (ML605). I am using the production hdl design + software. It runs by your help .
Now I like to simulate something to understand the behavior of the design much better. So, the Design is okay. Here are my steps to do this:
1) In EDK I selected "Project" -> "Project Options" -> "Design Flow"
x Treat timing closure failure as an error
x generated test bench tamplate
2) added elf-Files (implementaion and simulation)
3) Generate HDL Files -> "... Simulation Model Generator done! Done! tun." ( No error occurs)
4) Launch Simulator -> "...Starting static elaboration. Done! tun. tun. .." ( No error occurs)
In other projects simulations are working on this way. So I think its an problem by your HDL-project?! Have you tried the simulation before? Do you have an idea to run simulation of the Design behavior? It's important for me for integrating a second Device in my design.
Thanks for your help.