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AD9467 PN9/23 Verification speeds

Question asked by bitwiselannon on Mar 11, 2014
Latest reply on Mar 13, 2014 by UmeshJ

Hi all,


my question is regarding the PN9/ 23 test modes for the AD9467 250Mhz ADC.


I understand how the pattern is generated (thanks to the other threads on this forum for clearing a few things up!). I wonder how people implement the verification of the data stream:


The ADC outputs a 16-bit word at 250MHz. Inside my fpga (Xilinx 7-series) I want to sample 23-bits then start generating the following bits, checking against what is being sent by the ADC.


In order to keep up with the incoming test stream real time, I have to calculate 16 new bits of the sequence per 4ns (250MHz). I can only see this being done sequentially so I'd need a 4GHz clock!?


Am I missing a clever way of doing this using the dsp/ shift register fabric on the FPGA without the need for such a fast clock, or is it typically implemented as 'buffer x samples -> verify everything in the buffer -> repeat'?


Thanks for your time.