Can you provide a code and details as to how to workaround this Anomaly on Boot .
Could you please provide me a Init code which as Workaround for the anomaly 05000490 for Silicon Rev 0.2 .
I have also referred to the following doc but could you provide the same for BF51x .
Does the present Init code present in VisualDSP++ 5.0 have the the workaround for this anomaly .
Could you please also late me know with regards case #3 .
What does this mean , should we check every device to check if the Anomaly wer to occur or not .
This Case#3 is unknown area how do we get to know with regards to this .
3) When system timing parameters allow for any single word to get transferred from the shift register to the SPI FIFO exactly as the SPI
port is being shut down, the anomaly can theoretically be encountered, though it has not been observed on silicon or in simulations. All
of the system timing parameters mentioned above must combine to cause the timing that triggers the anomaly.
With best regards and wishes