I have a ZC702 eval board and an AD-FMCOMMS3 board. When I run the console program in no-OS driver of AD9361, I found the BBPLL clock cannot be locked. As the following code (from “util.c”) shows, the round_rate is 983.04MHz. The function ad9361_bbpll_set_rate sets this frequency into hardware. Inside this function, the calibration is done successfully (0x05E==1). Then ad9361_bbpll_recalc_rate reads out the frequency from the registers. It should return the frequency “983.04MHz” if the BBPLL is locked. But it seems like it is not locked, because the value is random at each running, such as 983.04MHz, 1143.04MHz or 343.04MHz. I don't understand why this issue occurs. Please help me. Thanks in advance!
from function "clk_set_rate()" in “util.c”
round_rate = ad9361_bbpll_round_rate(clk_priv, rate, &phy->clks[clk_priv->parent_source]->rate);
ad9361_bbpll_set_rate(clk_priv, round_rate, phy->clks[clk_priv->parent_source]->rate);
phy->clks[source]->rate = ad9361_bbpll_recalc_rate(clk_priv,