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ADV8003 t57 and t59 description question

Question asked by luckybear on Mar 6, 2014
Latest reply on Mar 7, 2014 by PaulS

ADV8003 datasheet t57 (same with t59) description is as active edge to data and control Start of data invalid, FPGA engineer said according to the description the timing should be -0.07ns or need to be described as data and control to active edge start of data invalid.

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To prove his idea, he lists ADV7604 datasheet t11 timing description. It is described as end of valid data to negative clock edge.

 

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So can you check and advise?

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