I received this question from a customer:
We are having problems with the AD5293 digital pot. We are having problems with it on a prototype board. It consistently locks up the SPI bus (specifically the MISO pin).
Initially, we took no precautions in powering it up. In our sequencing, the likely power sequence was: GND, VDD & VSS (+12V and -12V), pot pins (around 2V), Vlogic (3.3V) and then SPI bus. As defined in the spec, the ideal power-up sequence is GND, VSS, Vlogic, VDD, SPI and finally pot pins. This sequence will be difficult to manage since the VDD and VSS power rails come up simultaneously. with the pot pins immediately behind this. Vlogic and the SPI bus come up next.
Other than simply meeting the ‘ideal’ sequence, what are the physical restraints? Is there a specific voltage limit per pin as it powers up, or simply a diode drop? Where should the pins be before power-up; weakly tied to ground? If I sent a schematic with the resulting power-up, would someone at Analog Devices verify that it will work properly?
We ran into similar issues with the AD5231 but simply isolating the SPI bus was sufficient. If I need to jump through too many hoops to use the AD5293, I am inclined to find an alternate or even redesign it out of the circuit.