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Chip damage from IOVDD low while I2C active?

Question asked by joe42 on Mar 3, 2014
Latest reply on Mar 6, 2014 by Yagami

This is a related to an old thread, but I wasn't sure if my response would be seen:

 

http://ez.analog.com/message/106256#106256

 

I can understand that having IOVDD (3.3V) powered down while SDA/SCL are high could lead to bus problems, but could it actually physically damage the chip?  I have a couple of dead ADAU1701's here that may have been subjected to this condition - I really see nothing else it could be as I try to debug the issue.  But I don't have strong evidence (yet) that this is what caused the failure.  I'm hoping I can either rule it out or blame the cause on this bad IOVDD state.  Can you clarify?  This wasn't answered definitively in the other thread.

 

(Failure mode:  1701 is disconnected from the microcontroller, but left connected to the EEPROM.  EEPROM seems fine to read manually, but any attempt at "link/compile/download" with the USBi results in SCL stuck low.  Haven't been able to talk to the 1701 at all after that, even after resets/power cycles.)

 

Thanks.

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