The source code in axi_ad9122.v
input [63:0] dac_ddata;
this port timing and how to use?
It is a FIFO- (search for FIFO interface)
dac_drd - use it to increment your FIFO read pointer.
dac_ddata - pass FIFO output to this input (latency is tolerated)
dac_dvalid - 1'b0 is good (obsolete)
dac_underflow - pass status (1'b0 if you don't care- software might need this).
In this case, all this need to run at DAC_CLK/4.
Retrieving data ...