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AD9650 Inverted CMOS Output

Question asked by Jaysxx on Feb 27, 2014
Latest reply on Mar 5, 2014 by Anthony.DeSimone

Is the AD9650 CMOS output inverted by default? By inverted I mean Gnd is 1 and DRVDD is 0. If yes, I must have missed something in the datasheet.

If not, I need to figure out  why my custom board with AD9650 is outputting inverted data. I thought I was configuring it incorrectly so I tested it with 'power-on defaults' which also produced inverted data. When I configured it for inverted data output by setting register '0x14' bit 1, it produced non-inverted data.

To make sure I was not inverting the data in the FPGA, I checked the adc output with a scope (with terminated input) and found that bit 15 was low (GND), bits 14,13 etc were high( DRVDD) and bits 0-3 bounce about.

Once I bitflip, the data look alright. If this is erroneous, I need to find out what is causing it. I have attached the schematic for the adc circuit.