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Algorithm for Multichip AD9361 phase calibration- Will it work?

Question asked by FreddyS on Feb 27, 2014
Latest reply on Mar 12, 2014 by Timo

Dear Supporter

We would appreciate your oppinion approving  us that the following  algorithm to calibrate the phase difference between 2 AD9361 without external source.

Refer to the attached diagram. Two AD9361 are used providing 4  transmission channels – TX output 1,2,3,4 and 4 receiving channels Rx input 1,2,3,4. Calibration is done at the RX and TX paths as described below:

 

Rx path- Calibration and operate modes

Calibration mode (In this mode we will work at FDD mode)

 

1.Each time we jump to F1 frequency we will transmit a signal at F1 frequency from Tx 2B output of transceiver 1 and receive signals at ports Rx2B of both Transceivers 1 and 2  . Internal LO is used.

2. We will measure Rx 2B  signals of   transceiver 1 and 2 ( I,Q).   We will calculate the phase difference ΔƟ_RX in our FPGA.

 

Operational mode (In this mode we will work at TDD mode (Using  Rx_1A )

 

3.  We will keep Tx LO signal at F1 and Rx_LO signal at F1. (We will set MCS RF Enable to keep dividers LO dividers on)

4. We will  set Rx channel to Rx 1A  at both transceivers 1 and 2. We will measure Rx 1A  signals of   transceiver 1 and 2 ( I,Q) and subtract from  those RX measurements  the phase difference  ΔƟRX measured on par 2.

 

Tx path -Calibration and operate modes

Calibration mode (In this mode we will work at FDD mode)

 

5. At the same time ( when we do par 1 ) we will transmit a signal  at F1  at Tx _1B  from both  transceiver 1 and 2 .

6. We will measure the received signals at ports Rx_1B of both Transceivers 1 and 2

7. We will calculate  the phase difference at F1 frequency between Rx 1B  signals of   transceiver 1 and 2. Let's call this phase difference ΔƟ_TX_RX

8. The phase difference between the Tx LO  signals of   transceiver 1 and 2  will be calculated at the FPGA as follows : ΔƟ_TX= ΔƟ_TX_RX- ΔƟ_RX ( from par 4)

 

Operational mode (In this mode we will work at TDD mode)

 

9.  We will keep Tx LO signal at F1. (We will set MCS RF Enable to keep dividers LO dividers on)

10. We will  set Tx channel to Tx 1A  at both transceivers 1 and 2. but with a phase difference ΔƟTX computed on par 8

 

Questions :

a) Do you see any problem with this block diagram or algorithm ?

b) What will be  TX LO leakage level  at Tx_ B port when we are  in receiving  mode in TDD mode.? What will be the leakage between Rx_B port to Rx_A ? I am concerned about  Tx_LO leakage from  Tx_2B  to Rx_2A via Rx2_B

Regards

Freddy

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