AnsweredAssumed Answered

problem to configure PLL

Question asked by ashu.deal on Jul 14, 2010
Latest reply on Jul 15, 2010 by gvasanth

Hi dear

I am new to blackfin , i am using BF561 ( dual core) EZ Kit lite.I am trying to program the PLL to see the system clock on

85 pin of J2 but the code is not working at all.it seems as i am unable to configure the PLL control register.

please any one can help. my code is as follows.

 

#include <defBF561.h>

#include <cdefBF561.h>

#include <sysreg.h>

#include <services/services.h>

#include <ccblkfn.h>

#include<stdio.h>

 

void main()

{

int j ;

 

 

adi_core_b_enable();

 

//Enable SCLK1 for asynchronous memory region accesses. So that we can probe on the SCLK1 signal

*pEBIU_AMGCTL=0x1;

asm("ssync;");

 

//PLL wake up

*pSICA_IWR0 = 0x0001;

asm("ssync;");

 

 

*pPLL_CTL = 0x1400 ;

asm("ssync;");

 

asm("cli r0;\    // PLL prog. sequence

idle;\

sti r0;");

 

*pPLL_DIV = 0x0006 ;

asm("ssync;");

 

*pFIO2_DIR = 0xFFFF;

while(1)

{

 

*pFIO2_FLAG_T=0xFFFF;

}

 

 

}

Outcomes