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AD7192 Problem with RDY

Question asked by mroush on Feb 26, 2014
Latest reply on Feb 26, 2014 by mroush

Using AD7192 with 2 load cells, 5V load cell excitation and AD7192 reference.

Using internal clock, measured at 4.95Mhz.

Using bi-polar differential mode.

Have tried two different parts with identical results.

After power up and reset (40 1's) I expect a 50 hz toggle on the RDY pin.  Instead I get exactly 1/4th or 12.5 hz.

I can change the MR9:0 bits in the mode register and always get an update rate of 1/4th what the formula says.

If I use the default mode register setting of 0x080060 I expect 4.95Mhz / 1024 / 96 = 50.3 hz and I actually get 12.5 hz.

If I use a mode register setting of 0x080040 I expect 4.95Mhz / 1024 / 64 = 75 hz and I actually get 18.88 hz.


Also, the RDY signal only goes low for about 1.1 usecs which sure doesn't allow much time to read out data.  I would expect RDY to be mostly low and only go high a short time befroe an update.  Seems almost like it is inverted.


I can read out data from one channel and it appears very stable and about what I expect from the load cell.  I can put weight on and off and the reading corresponds to the predicted value.


I have checked all the SPI signals on a scope and everthing looks normal.  Falling edge of SCLK is when data changes and rising edge is clocking in data.  SCLK idles high between transfers as recommended.


Does anyone have any idea of what I am doing wrong?