This is on a 21469. It seems as though I can get code to run on this DSP despite having floating CLK_CFG pins, however when testing the internal clocks I've noticed I am unable to produce valid results. CLKIN is 24.576MHz and no matter what I do with PMCTL following example code, I cannot get a good CCLK or PCLK.
I've tested this in the following ways:
(i) I verified CLKIN was 24.576MHz by sending a PCG BCLK with divider 1 out the SRU.
(i) I scoped PCLK by setting PCG CLKA_SOURCE_IOP and sending it out the SRU.
PCLK was 24.576/2 MHz despite the fact that CCLK should have been 24.576MHz*18.
Would having floating CLK_CFG pins prevent me from setting the CCLK in software during runtime?