I am using the FMCOMMS1 and the zc702 eval board.
What is the logic for the test mode patterns “0100”, alternating checkerboard? I’m running the part in “parallel interleaved” mode. I get the following patterns.
A – channel A
B – channel B
A-0x1555 B-0x2AAA A-0x2AAA B-0x1555 A-0x1555 B-0x2AAA…
A-0x2AAA B-0x1555 A-0x1555 B-0x2AAA A-0x2AAA B-0X1555…
A-0x1555 B-0x1555 A-0x2AAA B-0x2AAA A-0X1555 B-0X1555…
A-0x2AAA B-0x2AAA A-0X1555 B-0X1555 A-0x2AAA B-0x2AAA…
So does the pattern really change on A to B transitions “and” B to A transitions or just one?
What is the logic for the test mode patterns “1111”, ramp output? I’m running the part in “parallel interleaved” mode. Sometimes I see the pattern get out of sync. Is this a problem in my “sampling” of the data or maybe in the AD9643?
Sometimes I see patterns like the following.
Are the A and B test pattern generators synchronized with each other? In the above, channel B is one count value behind A.
Is it not safe to assume the A and B test patterns are synchronized?