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AD9361 BBPLL lock

Question asked by Raveendra on Feb 21, 2014
Latest reply on Feb 24, 2014 by tlili

Hi,

 

I  am also trying to initialize the chip for the first time using FPGA(Spartan6).

The first thing i did is to configure CLK_OUT the same as the reference input, CLK_OUT is ok.

Then i tried to configure the BB PLL. I am trying to configure BBPLL to generate 800MHz, such that my ADC_CLK is 25MHz by using 32 divider and the reference frequency is 40MHz. Data_Clk I am expecting is 3.125MHz.

 

After configuring the chip, I am not getting CLK_OUT and BBPLL is also not getting locked. Can you please help me to overcome this.

 

Here i attached the register sequence i followed up to BBPLL config.

 

Regards,

Raveendra

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