Hello, I am attempting to use the FMCOMMS2 board with the Zedboard.
I checked out the hdl code from https://github.com/analogdevicesinc/fpgahdl_xilinx.git (tag ad_fmcomms2_ebz_edk_14_4_2013_10_22) and am attempting to generate the Xilinx netlist files from xco using ISE 14.4 as per the instructions in http://wiki.analog.com/resources/eval/user-guides/ad-fmcomms1-ebz/reference_hdl .
But some of the cores crash ISE 14.4 on RHEL 6, and give an error with ISE 14.4 on Windows 7 - I have included the exact errors below. For instance, the ad_dcfilter_1.xco file . The problem seems to be that the dsp48 macro version 2.0 and 2.1 do not support Zynq, and the first version that supports Zynq is version 3.0, which works with Vivado.
I have been stuck on this problem for a few days. I tried to generate the dsp48 core myself (for instance, the ad_dcfilter_1 xco uses the instruction (D-A)*B+C, but it doesn't work because some of the options are not available for Zynq - it doesn't allow setting the bitwidth of the D input to 16).
Can you please let me know how I should proceed? Thanks!
Error in RHEL 6 before ISE crashes:
"cf_lib/edk/pcores/adi_common_v1_00_a/netlist/ad_dcfilter_1.xco", ISE 14.4 crashes with the following message:
"FATAL_ERROR:GuiUtilities:Gui_Clip_ApplicationBase.c:369:1.30 - No index entry
for empty element ID. This application has performed an illegal operation and
must be shut down. Process will terminate. For technical support on this
issue, please open a WebCase with this project attached at
Error in Win 7: A Xilinx application has encountered an unexepcted error... No index entry for empty element ID."
with the following message in the "Information" tab: ERROR:sim:879 - Part'xc7z020-1clg484' is not valid for component 'xilinx.com:ip:xbip_dsp48_macro:2.0'.