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Question asked by TriGuy1 on Feb 21, 2014
Latest reply on Mar 11, 2014 by TriGuy1

Scenario 1: We are driving the ADV7612 EDID pins with the DDC output pins of the AD8192 that are pulled up to +3.3V. We see +5V DDC Data and Clock at the input to the AD8192 and the same Data and Clock lines at the output, except they are pulled up to +3.3V. The signal quality seems to be fine. This scenario leads to NOT being able to read EDID from of the ADV7612. We are getting a NAK on the data line.


Scenario 2: Using the exact same setup for the ADV7612, we removed the AD8192 from the scenario and directly drove the ADV7612 EDID pins from the source. The data and clock lines were pulled up to +5V. We did not see any significant difference in timing between the DDC clock and data lines between either scenario. Using scenario 2, we were constantly being able to read correct EDID information.


We are not using 5V detect so in both scenarios all of the 5V_DET register's are disabled. A sample of our EDID implementation is provided in the attached schematic.


The VIH for the ADV7612 DDC pins is 2.6V. When using the AD8192, the DDC pins are pulled up to a +3.3V. Could this be a problem?

Could someone provide other recommendations to try out?