Although I cannot find any documented reference to it, I am finding that the FIR Accelerator is consuming some core cycles. It's not much, but enough to prevent some demanding audio processing from completing on time.
I have a project which runs on custom hardware which demonstrates the problem very clearly if I use the core to simply toggle a flag in a loop, and measure the time it takes for each transition of the flag using a 'scope. I am finding that this time varies by as much as 20%. It is highest immediately after starting the Accelerator.
The attached project for the ADSP-21498 EZ-Board also demonstrates the issue, albeit slightly less clearly. This is the best I can do without spending much more time on an EZ project.
In main(), I am toggling flg2 (P2.39), and outputting a synchronising trigger on flg3 (P2.40) each time we restart the Accelerator.
Analysing the scope traces, I can see that flg2 toggles every 388ns just after starting the Accelerator (Trace ..7 attached), but reduces to 376ns just before we are about to restart the Accelerator again (Trace ..6 attached). A difference of about 3% in this particular demonstration.
I have been careful to make sure, both in the project used on the custom hardware, and the project used on the EZ Board, that interrupts are not causing these timing anomalies.
Is there a known (documented) reason for the Accelerator to consume core cycles in this way?