I would like to know if the AD9361 is suitable for non-0 IF applications. As it seems that the filters are low pass, this need to be done not using any possible IF but (if the receiver is subject to adjacent channel interference, etc.) to allow rejection with low pass, a range of IF close to DC, not very different from fIF=1/2 (BWmax), that for many practical implementations with economy of sampling speed will be the same as fs/4 being fs the sampling rate. This arrange is common when one needs to avoid 0 IF for any reason (LO interference, DC or quasi DC issues or offsets, Doppler, etc.) keeping still the lowest sample rate possible, and allow to build a receiver/demodulator without the need of a bandpass.
If this is possible, and the programming of the chip is versatile enough to accept it and not taking 0-IF for ganted, there are two other main issues:
- with non-0 IF, image rejection is needed. The AD9361 demodulators are IQ, and so, it should be possible to configure them as image rejection heterodyne down converters (instead homodyne converter) depending on the exact implementation of the demodulatros and the capabilities of the processor. Again, it depends on whether the AD9361 control is ready for these tasks. Also there can exist HW restrictions as far as for this functionning there are certain steps in the IF processing that must be done before any other thing, and must be done before the A to D conversion. (basically, wide band phase shifting). Maybe this is not possible, and thus the AD9361 architecture would not be suitable for this application.
- strict analog and digital low pass filtering enough to reduce adjacent channels and images in analog and reduce them to below the target SINAD in digital. It means at least 10 dB rejection in a few 100's Khz from the BW limit in analog and 50 to 60 dB in digital.Can you tell me if the selectivity is possible and if a strict FIR filter can be programmed or at least can be implemented outside the chip.
We are considering the possibility of using of the chip as an on channel repeater (transmitting the same Rx channel at the same frequency), so the total delay from Rx to Tx is limited to a min. for causality in certain processes and to a max. for network interference issues. This can affect also the possibility of the chip application. I didn't start by here as far as I have assumed that this is possible for AD9361. Typical acceptable total delays are from a few to about 10 us.
Finally, in case that non 0-IF applications are not recomendded o possible at all with AD9361, my final point is that we can move our application to a 0-IF architecture, but in this case we need to be sure that the Rx and Tx performance is not worst compared with the heterodyne as a result of the LO to RF and LO to Tx Rx chip leakages. In particular The Tx LO rejection in our applications is really critical. Concerning Rx, in the application the signal will not be demodulated on board so any LO leakage is to be repeated so it just accumulates dor Tx degradation.