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ADF4351 PLL lock time and step size

Question asked by Raveendra on Feb 19, 2014
Latest reply on Feb 26, 2014 by rbrennan

Hi,

I am planning to use ADF4351 PLL in my circuit. i want to know one thing about what will be locking(settling) time of PLL and what minimum step size is possible?

 

My operating frequency range is 1300-1800 MHz and  step size is 10 Hz.

 

If it possible kindly suggest the which reference freq, loop filter bandwidth and PFD frequency.

 

Please help to reach my requirements.

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