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LRCLK, BCLK buffering? EMC aspects

Question asked by jorpese on Feb 18, 2014
Latest reply on Feb 20, 2014 by jorpese

Hi, I am designing an audio system with a DSP and 4 converters: 2 AD1939 (master and slave) and 2 AD1974 (both AUX to the 39s). One of the AD1939 is the TDM master. To reduce the number of lines and facilitating the routing, the rest of codecs are using the PLL in LRCLK and, accordingly, BCLK is not transmitted to the rest of codecs.


The DSP is carried on a module that plugs into the board. The distance between the DSP and the codecs could be between 6 and 10 cm. Between the master codec and the slave '39 could be up to 4cm.


The master AD1939 generates a 48kHz LRCLK and a 12.2880MHz BCLK. LRCLK is supplied to two DSP inputs and to the slave AD1939. BCLK is just sent to two inputs to the DSP.


I use a IDT5T30553DCGI to distribute LRCLK and BCLK. According to its spec sheet, the rise times can be 1ns max. Because of that rise time I have back terminated the lines with a series 33Ω resistor to reduce the reflections. The material will be FR4 and the line impedance around 50Ω.


This audio board has also ethernet and the analogue audio I/O stages as well. In addition, the board is sitting in a tray with other boards like HD analogue video. Should I worry about EMC aspects in the audio board or adjacent? The edges will create emissions starting on 350MHz so it should not affect the rest of circuitry as it is way up in the spectrum.


Providing that I do not need to pass any EMC compliance tests or similar, should I worry for those ultra short edges? Am I being too paranoid and it is just fine? Am I creating a problem by buffering the LRCLK and BCLK signals with those ICs and I should not use anything at all?


Thank you very much in advance.