I am using a AD9956 to generate a 500MHz clock (CML) from an ultra stable 10MHz source. This clock signal should be distributed to different AD9910 DDS (this chip because of the parallel capabilities). On the website I could find a LVPECL clock fan out buffer ADCLK954. I was wondering if this is an appropriate distribution IC considering the output level and low phase noise or if you have other recommendations.
One follow up question: As far as I can see, the phase noise performance of the AD9956 is limited by the phase noise of the PLL (I measure -70dBc @ 10Hz). Do you have any suggestions on how to create a RF source (some hundred MHz) from an ultra stable 10MHz source with less phase noise.