- 1. We're using zed board with FMCOMM2.
- 2. The version of Xilinx ISE/ XPS we are using is 14.4
- 3. When we open the cf_ad9361_zed, we see the error as in "error_upon_opening_system.png".
- 4. We then generate the net lists as given in procedure "http://wiki.analog.com/resources/eval/user-guides/ad-fmcomms1-ebz/reference_hdl".
- 5. When generating net lists, in the above link in S.No.4, it is mentioned as "Under the “Part” tab, select family: “Virtex6”, Device: “xc6vlx240t”, package: “ff1156” and Speed Grade: ”-1”. This corresponds to ML605. You may use this same selection, even if you are targeting a KC705 or ZC702 board. Click on “Apply”." It is therefore assumed that though it is Zynq, the part selection does not change. Is it really so, please confirm if there is a concern here.
- 6. After generating the netlists, we copy the netlist and .v files into the respective directories in pcores folder and run "generate netlist" in xps.
- 7. We get errors as in "errors_generatenetlist.rtf". The netlist does not generate.
- 8. We have also done a rescan hardware after inserting the netlist and .v files. Does not help.
Appreciate your help in resolving this