I use AD9525 in my design. I meet a problem that confused me.
As known, AD9525 is configured through SPI bus, which contain SCLK, SDIO, SDO and CS lines. In my design, I use five AD9525 chips, and I connect the five chips with SCLK and SDIO lines. When I configure a specific chip, I select the chip using CS pin.
The SPI bus is controlled by FPGA(as master). When I test the SCLK and SDIO signal with oscilloscope, the signal showed a wrong shape. As is showed in attachment. In the one side, the amplitude of the signal is about 2.0V, which is below the FPGA OBUF standard of LVCMOS33. On the other hand, there be likely a ring on the signal. What's the possible for this error?
Besides, I also test the CS signal when in configuration, and the signal on this line is correct.