I apologize in advance for the length of this post! I have a quite a few questions here, so feel free to respond to them individually.
We’re designing a product that will use the ADuM6210 with 5V input and 5V output to power another digital isolator (ADuM3482) and a few ADC chips. Our max output current will be 24mA. App note AN-0971 describes a number of concerns about high frequency emissions that would affect our certification and layout techniques to address them, but for practical reasons we won’t be able to follow those recommendations exactly, and I’m wondering what the consequences of that will be. We’ll also need to meet the tightest emissions requirements as we’ll be certifying this product internationally:
- AN-0971 is based on an ADuM540x series chip running at 100mA. The graphs show a linear relationship between mA output and emissions levels. We're using an ADuM621x chip that will run at a max current output of 24mA. Will the emissions of this chip be consistent with those shown in the app note for the ADuM540x running at 30mA output? Specifically I'm referring to Figures 22 and 23 in the app note.
- My guess is that this will be true for the 360MHz emissions (250MHz for the 621x which switches at 125MHz instead of 180MHz) because according to the app note, those are directly related to the output current and hopefully the relationship is the same for the 621x. But for the 180MHz emissions (125MHz for the 621x) I'm worried that they will be the same as they would be at 77mA for the 540x because these are based more on the duty cycle, which would be 77% in our case (the 621x’s max output current is 30mA). Of course, the input current should be lower on the 621x, but it isn’t exactly clear how much of a effect that would have on the emissions.
- Will the different switching frequency of the 621x (125 MHz instead of the 180MHz of the 540x) have any effect on the magnitude of the emissions?
- Does the edge guard need to cover the entire board to be effective, or can it be limited to the region immediately surrounding the isolators? We’re planning to put it on both the primary and secondary side to be conservative.
- Can the noise-cancelling effect of inter-plane capacitance be realized on a 4 layer board by placing layers 1 and 2 close to each other and layers 3 and 4 close to each other (ie. thin pre-preg and thick core) and making layer 1 Signal/GND FIll, Layer2 PWR Fill, Layer3 GND Fill, Layer 4 Signal/PWR Fill? We want to do this to minimize the emissions from other higher frequency traces in different regions on our product, but the recommendation in AN-0971 is to place layers 2 and 3 close together.
- I understand that stitching capacitance is the most effective way to reduce the emissions, but given our board geometry and safety requirements, our max dimensions for the overlap area are: L=60mm, w=20mm, d=0.5-1.0mm, which gives us a best case capacitance of only 45pF to 90pF, using FR4 as our core material. Looking at Figure 20 of AN-0971, this small of a capacitance offers almost no improvement for the 180MHz emissions (which would be 125MHz in our case) and only about 10 dBuV/m of attenuation for the 360MHz emissions (which would be 250MHz in our case and hence would probably see even less attenuation). Would a width of 20mm still be beneficial, or does the benefit of extra width decrease once the width is beyond that of the chip (about 6mm)?
- We could also add a discrete safety capacitor, but according to the app note, they have limited effectiveness over 200MHz, so we'd only be able to rely on that for attenuating the 125MHz emissions on our board. Does the effect of these capacitors tend to stack as more capacitors are added? Or does the inherent inductance in the pads, vias, etc. limit their effectiveness such that there's no point in adding more than one?