Planning on using Mode 10 and 11 that allows for PIP overlay with alpha blend, which is what we want to use the chip for.
But concerned about one part of those diagrams...
They show that you can input the PIP using the OSD video input at just about any resolution; however, internally it then shows that the OSD path scales down to 480 going through the secondary VSP and then back to the final video output resolution via the Scale OSD block.
QUESTION 1. Does this imply that the OSD path MUST scale down to 480 internally? Or can we keep the OSD path at native resolution until it finally scales to the output resolution for alpha blending?
Also, we are considering using multiples of these chips ganged together with their outputs going into an FPGA for pixel-level final mixing of 4 video PIPs on one background PC graphic. In order to make this architecture work with a small-ish FPGA we need the outputs of four ADV8003 chips to all be synchronized at the pixel level—meaning that the v-syncs are aligned and pixel clocks basically aligned.
We're planning to feed the identical primary video source into all of the ganged chips with different OSD video sources so that we can implement a final mix in the FPGA with multiple PIPs using a cut-out approach. So part of our evaluation is to figure out how the DPLL in the chip is going to react to this concept. I can see that there are a couple of different modes for the DPLL "Frame Tracking" which involve either "phase lock" or "frequency lock". With phase lock it holds the output until the next v-sync which would be great for aligning the outputs of multiple chips but then we suffer from a frame of latency. Extremely low latency is a requirement. With the frequency lock it sounds like the latency will be largely removed but then I fear that with multiple chips we may have their outputs not pixel-by-pixel aligned. For example I'm afraid that the offset of each chip may depend on when the I2C commands are given to the chip to start the video pipeline, etc.
QUESTION 2. From the description above, is the multiple ADV8003 device architecture possible? Are there tips/methods to keep the frame/pixel clocks aligned and insure the low latency requirement that I’m needing? Can I accomplish this in several ADV8003s and keep my FPGA requirement small?
At this point of the evaluation I'm leaning toward the ADV8003 chip being a good candidate for use as an HDMI/DVI output processing chip but I'm growing more skeptical that we can take the risk on using it for the ganged inputs to obtain our desired 4-PIP architecture. Can you think of some way that we could boost our confidence in using the chip in this way? I'm sure you'd like us to use five of these chips instead of one per board and so would we since it greatly reduces our FPGA size if we can do the front-end scaling in the ADV8003 chip.