As long as I obey the pin setup and pin hold timing constraints for IO_UPDATE, can I drive IO_UPDATE and CSB
with the same signal?
BTW, the constraints on IO_UPDATE seem fishy to me. They are specified in terms of SCLK, the SPI serial clock,
which has (in CPOL=0 mode) returned low and is inactive when the IO_UPDATE's rising edge should occur.
I can understand a timing specification in terms of SYSCLK, but SCLK? What am I missing?