I have a question about CLI and STI
I have 4 different SPI circuits in my hardware design (AD, DA, FRAM and a Display)
My application architecture is a main loop and 2 interrupt routine.
The main loop executes every 30 second, and one of the interrupts is a timer interrupt that
executes 200 times/second.
My problem is that i have to access the SPI bus both in my main loop and in my timer ISR, and
sometimes the timer ISR interrupt my current SPI transfer with it's own SPI access.
My question is if it's possible to guard all SPI transfers with CLI/STI ??
Will my timer ISR be triggered after the STI, or will i miss interrupts
between the CLI/STI section ??