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ADV7511 PLL not locking

Question asked by bmissele on Feb 12, 2014
Latest reply on Feb 22, 2015 by shivncetec067@gmail.com

We have designed a board using an FPGA to drive video to an ADV7511. We used the Xilinx ZC702 Evaluation platform schematics as a reference. Our ZC702 eval board works, but when we run the same register settings on our board, we can not get the PLL to lock. Ripple noise on the 1.8V inputs looks reasonable and the clock signal integrity also looks good on a scope. We are using the following register settings:

 

  (Slave Addr, Reg Addr, Write Data)


      (HDMI_TRANS_ADDR, x"D6", x"c0"),   -- check for HPD high (will poll until high)

      (HDMI_TRANS_ADDR, x"41", x"10"),   -- power on HDMI transmitter

      (HDMI_TRANS_ADDR, x"98", x"03"),   --

      (HDMI_TRANS_ADDR, x"9a", x"e0"),   --

      (HDMI_TRANS_ADDR, x"9c", x"30"),   --

      (HDMI_TRANS_ADDR, x"9d", x"61"),   --

      (HDMI_TRANS_ADDR, x"a2", x"a4"),   --

      (HDMI_TRANS_ADDR, x"a3", x"a4"),   --

      (HDMI_TRANS_ADDR, x"e0", x"d0"),   --

      (HDMI_TRANS_ADDR, x"f9", x"00"),   --

      (HDMI_TRANS_ADDR, x"15", x"05"),   -- RGB 4:4:4 DDR separate syncs

      (HDMI_TRANS_ADDR, x"16", x"3a"),   -- [1:0] = "10" (rising edge first pix), [3:2] = "10" color style 1, [5:4] = "11" (8 bit)

      (HDMI_TRANS_ADDR, x"17", x"00"),   -- hsync/vsync polarity high.

      (HDMI_TRANS_ADDR, x"48", x"30"),   -- left justified, DDR in [36:18]

      (HDMI_TRANS_ADDR, x"af", x"04"),   -- DVI out mode

      (HDMI_TRANS_ADDR, x"56", x"14"),   -- AVI info frame - 4:3



Then I read back the registers and get the following:


      (Slave Addr, Reg Addr, Read Data)


      (HDMI_TRANS_ADDR, x"41", x"10"),   -- power on HDMI transmitter

      (HDMI_TRANS_ADDR, x"98", x"03"),   --

      (HDMI_TRANS_ADDR, x"9a", x"e0"),   --

      (HDMI_TRANS_ADDR, x"9c", x"30"),   --

      (HDMI_TRANS_ADDR, x"9d", x"61"),   --

      (HDMI_TRANS_ADDR, x"a2", x"a4"),   --

      (HDMI_TRANS_ADDR, x"a3", x"a4"),   --

      (HDMI_TRANS_ADDR, x"e0", x"d0"),   --

      (HDMI_TRANS_ADDR, x"f9", x"00"),   --

      (HDMI_TRANS_ADDR, x"15", x"05"),   -- RGB 4:4:4 DDR separate syncs

      (HDMI_TRANS_ADDR, x"16", x"3a"),   -- [1:0] = "10" (rising edge first pix), [3:2] = "10" color style 1, [5:4] = "11" (8 bit)

      (HDMI_TRANS_ADDR, x"17", x"00"),   -- sync mode

      (HDMI_TRANS_ADDR, x"48", x"30"),   -- left justified, DDR in [36:18]

      (HDMI_TRANS_ADDR, x"af", x"04"),   -- DVI out mode

      (HDMI_TRANS_ADDR, x"56", x"14"),   -- AVI info frame - 4:3


      (HDMI_TRANS_ADDR, x"3d", x"48"),   -- pixel rep x2, VIC#8: 240p-60, 2x Clk, 4:3

      (HDMI_TRANS_ADDR, x"3e", x"00"),   -- VIC unavailable

      (HDMI_TRANS_ADDR, x"3f", x"B0"),   -- 240p active, 263 lines

      (HDMI_TRANS_ADDR, x"d5", x"00"),   -- high refresh rate

      (HDMI_TRANS_ADDR, x"fb", x"00"),   -- low refresh rate

      (HDMI_TRANS_ADDR, x"9e", x"00"),   -- pll lock(NO PLL LOCK!!!)

      (HDMI_TRANS_ADDR, x"a1", x"00"),   -- chan power up/down(all up)

      (HDMI_TRANS_ADDR, x"c8", x"01")    -- Waiting for EDID


I am driving 800x600 video in with a 50Mhz Video clock.  The

frame rate is roughly 72Hz.

 

Any help would be appreciated.

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